1. Field of the Invention
This invention relates generally to the formation of integrated structures and circuits on semi-conductor substrates and more particularly to the formation of FET structures and circuits. In even more particular aspects, this invention relates to formation of CMOS FET structures and circuits on semi-conductor substrates and especially to pillar CMOS technology which utilizes both vertical and horizontal surfaces on which to form FET devices.
2. Background Information
One technique of increasing integrated circuit density on a given size semi-conductor substrate is by using vertical surfaces on which to form at least a portion of devices such as FET's. One form this takes is so-called pillar technology in which epitaxial silicon crystals or "pillars" are grown on a single silicon crystal substrate and the sidewalls of the grown epitaxial silicon "pillars", are used to form at least part of some of the devices, thus allowing increased integrated circuit density, i.e. more devices per horizontal surface of the substrate, without necessity of reducing the layout ground rule size. This permits the use of coarser lithography as well permitting greater channel length control, both of which are desirable results in integrated circuit technology.
The present invention provides an improved technique and resulting devices in pillar CMOS technology.